With increasing demands for faster processing capabilities in electronics such as computers, cell phones, and personal digital assistants (PDA's), minimizing energy dissipation has become a primary concern for integrated circuit design. In fact, due to size, space, and heat constraints, energy dissipation is increasingly becoming a limiting factor for high speed digital design.
Current trends to minimize active energy dissipation (i.e., the energy dissipated when transistors are switching) include varying the size of the transistors in a circuit, using a multiple-threshold design (e.g., providing low threshold transistors in critical paths), clock gating (e.g., shutting down the clock in portions of the circuit), and frequency scaling (e.g., slowing down the clock rate). In conjunction with varying the size of the transistors, an effective method for reducing the energy consumption in an integrated circuit is to scale down the supply voltage of the transistors. Scaling the supply voltage advantageously reduces the energy dissipation in the circuit because the energy consumption increases with the square of the supply voltage. As the supply voltage decreases, however, noise margins decrease and the integrated circuit becomes prone to malfunction. In addition, voltage scaled transistors have reduced drive capability, which results in slower operation. Therefore, the embodiments disclosed hereinafter were developed in light of these and other drawbacks.